Alif Semiconductor /AE512F80F55D5AS_CM55_HP_View /ETH /ETH_MAC_CONFIGURATION

Receiver Enable When this bit is set, the Rx state machine of the MAC is enabled for receiving packets from the RMII interface. When this bit is reset, the MAC Rx state machine is disabled after it completes the reception of the current packet. The Rx state machine does not receive any more packets from the RMII interface.

0 (Val_0x0): Receiver is disabled

1 (Val_0x1): Receiver is enabled

Transmitter Enable When this bit is set, the Tx state machine of the MAC is enabled for transmission on the RMII interface. When this bit is reset, the MAC Tx state machine is disabled after it completes the transmission of the current packet. The Tx state machine does not transmit any more packets.

0 (Val_0x0): Transmitter is disabled

1 (Val_0x1): Transmitter is enabled

Preamble Length for Transmit packets These bits control the number of preamble bytes that are added to the beginning of every Tx packet. The preamble reduction occurs only when the MAC is operating in the full-duplex mode.

0 (Val_0x0): 7 bytes of preamble

1 (Val_0x1): 5 bytes of preamble

2 (Val_0x2): 3 bytes of preamble

Deferral Check When this bit is set, the deferral check function is enabled in the MAC. The MAC issues a Packet Abort status, along with the excessive deferral error bit set in the Tx packet status, when the Tx state machine is deferred for more than 24,288-bit times in 10 or 100 Mbps mode. The defer time is not cumulative. For example, if the transmitter defers for 10,000-bit times because the ETH_CRS_DV signal is active and the ETH_CRS_DV signal becomes inactive, the transmitter transmits and collision happens. Because of collision, the transmitter needs to back off and then defer again after back off completion. In such a scenario, the deferral timer is reset to 0, and it is restarted. When this bit is reset, the deferral check function is disabled and the MAC defers until the ETH_CRS_DV signal goes inactive. This bit is applicable only in the half-duplex mode.

0 (Val_0x0): Deferral check function is disabled

1 (Val_0x1): Deferral check function is enabled

Back-Off Limit The back-off limit determines the random integer number ® of slot time delays (512-bit times) for which the MAC waits before rescheduling a transmission attempt during retries after a collision.n = retransmission attempt. The random integer r takes the value in the range 0 <= r < 2^k This bit is applicable only in the half-duplex mode.

0 (Val_0x0): k = min(n, 10)

1 (Val_0x1): k = min(n, 8)

2 (Val_0x2): k = min(n, 4)

3 (Val_0x3): k = min(n, 1)

Disable Retry When this bit is set, the MAC attempts only one transmission. When a collision occurs on the RMII interface, the MAC ignores the current packet transmission and reports a Packet Abort with excessive collision error in the Tx packet status. When this bit is reset, the MAC retries based on the settings of the BL field. This bit is applicable only in the half-duplex mode.

0 (Val_0x0): Enable retry

1 (Val_0x1): Disable retry

Disable Carrier Sense During Transmission When this bit is set, the MAC transmitter ignores the RMII ETH_CRS_DV signal during packet transmission in the half-duplex mode. As a result, no errors are generated because of Loss of Carrier or No Carrier during transmission. When this bit is reset, the MAC transmitter generates errors because of Carrier Sense. The MAC can even abort the transmission.

0 (Val_0x0): Enable carrier sense during transmission

1 (Val_0x1): Disable carrier sense during transmission

Disable Receive Own When this bit is set, the MAC disables the reception of packets when the ETH_TXEN signal is asserted in the half-duplex mode. When this bit is reset, the MAC receives all packets given by the PHY. This bit is not applicable in the full-duplex mode.

0 (Val_0x0): Enable receive own

1 (Val_0x1): Disable receive own

Enable Carrier Sense Before Transmission in Full-Duplex Mode When this bit is set, the MAC transmitter checks the ETH_CRS_DV signal before packet transmission in the full-duplex mode. The MAC starts the transmission only when the ETH_CRS_DV signal is low. When this bit is reset, the MAC transmitter ignores the status of the ETH_CRS_DV signal.

0 (Val_0x0): ECRSFD is disabled

1 (Val_0x1): ECRSFD is enabled

Loopback Mode When this bit is set, the MAC operates in the loopback mode at RMII.

0 (Val_0x0): Loopback is disabled

1 (Val_0x1): Loopback is enabled

Duplex Mode When this bit is set, the MAC operates in the full-duplex mode in which it can transmit and receive simultaneously.

0 (Val_0x0): Half-duplex mode

1 (Val_0x1): Full-duplex mode

Speed This bit selects the speed mode. Its value along with the PS bit value is also reflected in the ETH_STAT0[MAC_SPEED_O] field.

0 (Val_0x0): 10 Mbps

1 (Val_0x1): 100 Mbps

Port Select This bit selects the Ethernet line speed. This bit, along with the FES bit, selects the exact line speed. Their value is also reflected in the ETH_STAT0[MAC_SPEED_O] field.

1 (Val_0x1): For 10 or 100 Mbps operations

Jumbo Packet Enable When this bit is set, the MAC allows jumbo packets of 9,018 bytes (9,022 bytes for VLAN tagged packets) without reporting a giant packet error in the Rx packet status.

0 (Val_0x0): Jumbo packet is disabled

1 (Val_0x1): Jumbo packet is enabled

Jabber Disable When this bit is set, the MAC disables the jabber timer on the transmitter. The MAC can transfer packets of up to 16,383 bytes. When this bit is reset, if the application sends more than 2,048 bytes of data (10,240 if JE is set high) during transmission, the MAC does not send rest of the bytes in that packet.

0 (Val_0x0): Jabber is enabled

1 (Val_0x1): Jabber is disabled

Watchdog Disable When this bit is set, the MAC disables the watchdog timer on the receiver. The MAC can receive packets of up to 16,383 bytes. When this bit is reset, the MAC does not allow more than 2,048 bytes (10,240 if JE is set high) of the packet being received. The MAC cuts off any bytes received after 2,048 bytes.

0 (Val_0x0): Watchdog is enabled

1 (Val_0x1): Watchdog is disabled

Automatic Pad or CRC Stripping When this bit is set, the MAC strips the Pad or FCS field on the incoming packets only if the value of the length field is less than 1,536 bytes. All received packets with length field greater than or equal to 1,536 bytes are passed to the application without stripping the Pad or FCS field. When this bit is reset, the MAC passes all incoming packets to the application, without any modification.

0 (Val_0x0): Automatic Pad or CRC stripping is disabled

1 (Val_0x1): Automatic Pad or CRC stripping is enabled

CRC stripping for Type packets When this bit is set, the last four bytes (FCS) of all packets of Ether type (type field greater than 1,536) are stripped and dropped before forwarding the packet to the application.

0 (Val_0x0): CRC stripping for type packets is disabled

1 (Val_0x1): CRC stripping for type packets is enabled

IEEE 802.3as Support for 2KB Packets When this bit is set, the MAC considers all packets with up to 2,000 bytes length as normal packets. When the JE bit is not set, the MAC considers all received packets of size more than 2KB as Giant packets. When this bit is reset and the JE bit is not set, the MAC considers all received packets of size more than 1,518 bytes (1,522 bytes for tagged) as giant packets. Note: When the JE bit is set, setting this bit has no effect on the giant packet status.

0 (Val_0x0): Support upto 2KB packet is disabled

1 (Val_0x1): Support upto 2KB packet is Enabled

Giant Packet Size Limit Control Enable When this bit is set, the MAC considers the value in the ETH_MAC_EXT_CONFIGURATION[GPSL] field to declare a received packet as Giant packet. This field must be programmed to more than 1,518 bytes. Otherwise, the MAC considers 1,518 bytes as giant packet limit. When this bit is reset, the MAC considers a received packet as Giant packet when its size is greater than 1,518 bytes (1522 bytes for tagged packet). The watchdog timeout limit, Jumbo Packet Enable and 2KB Packet Enable have higher precedence over this bit, that is the MAC considers a received packet as Giant packet when its size is greater than 9,018 bytes (9,022 bytes for tagged packet) with Jumbo Packet Enabled and greater than 2,000 bytes with 2KB Packet Enabled. The watchdog timeout, if enabled, terminates the received packet when watchdog limit is reached. Therefore, the programmed giant packet limit should be less than the watchdog limit to get the giant packet status.

0 (Val_0x0): Giant packet size limit control is disabled

1 (Val_0x1): Giant packet size limit control is enabled

Inter-Packet Gap These bits control the minimum IPG between packets during transmission. This range of minimum IPG is valid in full-duplex mode. In the half-duplex mode, the minimum IPG can be configured only for 64-bit times (IPG = 100). Lower values are not considered. When a JAM pattern is being transmitted because of backpressure activation, the MAC does not consider the minimum IPG. The above function (IPG less than 96-bit times) is valid only when the ETH_MAC_EXT_CONFIGURATION[EIPGEN] bit is reset. When EIPGEN is set, then the minimum IPG (greater than 96-bit times) is controlled as per the description given in the ETH_MAC_EXT_CONFIGURATION[EIPG] field.

0 (Val_0x0): 96-bit times IPG

1 (Val_0x1): 88-bit times IPG

2 (Val_0x2): 80-bit times IPG

3 (Val_0x3): 72-bit times IPG

4 (Val_0x4): 64-bit times IPG

5 (Val_0x5): 56-bit times IPG

6 (Val_0x6): 48-bit times IPG

7 (Val_0x7): 40-bit times IPG

Checksum Offload When set, this bit enables the IPv4 header checksum checking and IPv4 or IPv6 TCP, UDP, or ICMP payload checksum checking. When this bit is reset, the COE function in the receiver is disabled.

0 (Val_0x0): IP header/payload checksum checking is disabled

1 (Val_0x1): IP header/payload checksum checking is enabled

ARP Offload Enable When this bit is set, the MAC can recognize an incoming ARP request packet and schedules the ARP packet for transmission. It forwards the ARP packet to the application and also indicate the events in the RxStatus. When this bit is reset, the MAC receiver does not recognize any ARP packet and indicates them as Type frame in the RxStatus. This bit is available only when the Enable IPv4 ARP Offload is selected.

0 (Val_0x0): ARP offload is disabled

1 (Val_0x1): ARP offload is enabled